Coding method and apparatus

ABSTRACT

An encoder includes a control bit insertion circuit (12) for inserting a control bit into input data, which is then subjected to I-NRZ modulation by a precoder (14) to generate a reference code. The reference code is given to a 4-code generation circuit (22) through a delay circuit (16), and frequency components of the reference code, and first, second and third codes generated on the basis of the reference code are detected by a frequency detector (18). The frequency components are given to a judge circuit (20) such that it is determined whether the frequency components are large or small. A judge signal is applied to the 4-code generation circuit and a frequency detector from the judge circuit. The 4-code generation circuit selectively outputs one selected from the reference code and the first to third codes on the basis of the judgement signal.

FIELD OF THE INVENTION

The present invention relates to a coding method and apparatus. Morespecifically, the present invention realtes to a coding method andapparatus used for a VTR, VCR, and etc. adopting a digital pilot signalrecording system so as to convert input data to which a control bit isadded at a head into an output code.

PRIOR ART

One example of conventional such a kind of coding apparatus is disclosedin, for example, Japanese Patent Application Laying-open No. 4-255969G11B20/14, H03M7/30! laid-open on Sep. 10, 1992. In the prior art,frequency components of two kinds of codes obtained by inserting acontrol bit of "0" or "1" at a head of input data of N+1 bits and bysubjecting the same to I-NRZ modulation, and an appropriate code isselectively outputted through comparison of processed results, and lasttwo bits of a selected code to a precoder for the I-NRZ modulation ofnext input data.

Since in such a prior art coding apparatus, the last two bits of theoutput code are fed-back, it is necessary to process preceding inputdata within a time that the input data equal to one code is modulated,e.g. a time period of 25 clocks in a case where one code is 25 bits soas to output the appropriate code, it is difficult to put the codingapparatus into practical use. More specifically, since a frequencycomponent extraction circuit performs Fourier transform for a DCcomponent and components of frequencies f1 and f2 in a modulated code, acircuit becomes quite large and a processing time for the extraction ofthe frequency components becomes long, it is quite difficult to shortena time period to extract the frequency components for one bit incomparison with a time period for the I-NRZ modulation of one bit data,therefore, and accordngly, it is difficult to put the coding apparatusinto practical use.

SUMMARY OF THE INVENTION

Therefore, a principal object of the present invention is to provide anovel coding mathod.

Another object of the present invention is to provide a coding method inwhich it is unnecessary to feed-back a portion of a preceding code.

A further object of the present invention is to provide a codingapparatus which implements the above described coding method.

According to the present invention, a coding method comprises steps of:(a) inserting a control bit into input data; (b) generating a referencecode on the basis of input data into which the control bit is inserted;(c) generating a predetermined number of associate codes on the basis ofthe reference code; and (d) selectively outputting one of the referencecode and the associate codes on the basis of frequency components of thereference code and the associate codes.

According to the present invention, a coding apparatus comprises:insertion means (12) for inserting a control bit into input data;reference code generation means (14) for generating a reference code onthe basis of data outputted from the insertion means; associate codegeneration means (22, 56a, 56b, 56c) for generating a predeterminednumber of associate codes being in correlation with the reference codeon the basis of the reference code; judgment signal output means (18,20) for outputting a judgment signal on the basis of frequencycomponents of the reference code and the associate codes; and codeoutput means (22, 54) for selectively outputting one of the referencecode and the associate codes according to the judgment signal.

In accordance with the present invention, since the associate codes aregenerated in advance on the basis of the reference code, and one code isselectively outputted on the basis of the frequency components of thesecodes, it is unnecessary to feed-back last two bits of a precedingoutput code, and therefore, a time restriction is released, andaccordingly, it is possible to certainly convert the input data into thecode.

In one embodiment, the judgment signal output means includes first toN-th extraction means for extracting first to N-th (N is an integer)frequency components of each of the reference codes and the associatecodes, first to N-th calculation means for calculating each of the firstto N-th frequency components, and outputting first to 2^(M) -th (M is apositive integer) calculation results, and first to 2^(M) -th operationmeans for operating each of the first to 2^(M) -th calculation resultsoutputted from the first to N-th calculating means.

In a case where frequency components are processed at every one code (ina case where M=1), frequency components of the reference code and afirst to third codes (the associate codes) generated on the basis of thereference code are extracted by frequency component extraction circuits,two of these frequency components are applied to a first and secondcomponent addition circuits included in, for example, a DC componentextraction circuit. Then, the first addition circuit functions as first,second, third and fourth addition means, and the second addition circuitfunctions as fifth, sixth, seventh and eighth addition means inaccordance with a change-over switch, for example. Therefore, thefrequency components are added each other, and outputs of the firstaddition circuit and the second addition circuit are outputted from a DCcomponent calculation circuit as the first calculation result and thesecond calculation result. These process is executed in the othercalculation circuits, e.g. f1 sine component extraction circuit, f1cosine component extraction circuit, f2 sine component extractioncircuit and f2 cosine component extraction circuit. Then, the firstcalculation result and the second calculation result outputted from thecalculation circuits are operated by a first square waiting additioncircuit and a second square waiting addition circuit, respectively, andthe operation results are applied to the judgment circuit. The judgmentcircuit judges sizes of the operation results, and outputs a judgmentsignal according to the sizes. The reference code is converted into apredetermined output code by, for example, a 4-code generation circuitaccording to the judgment signal.

The foregoing and other objects, features, aspects and advantages of thepresent invention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an illustrative view showing an operation of an I-NRZmodulation.

FIG. 2 is an illustrative view showing an operation of the I-NRZmodulation;

FIG. 3 is an illustrative view showing an operation of the I-NRZmodulation;

FIG. 4 is a block diagram showing one embodiment according to thepresent invention;

FIG. 5 is a block diagram showing a portion of FIG. 4 embodiment;

FIG. 6 is a block diagram showing a portion of FIG. 4 embodiment;

FIG. 7 is a block diagram showing a portion of FIG. 4 embodiment;

FIG. 8 is a block diagram showing a portion of FIG. 4 embodiment;

FIG. 9 is a block diagram showing a portion of FIG. 4 embodiment;

FIG. 10 is a block diagram showing a portion of FIG. 4 embodiment;

FIG. 11 is a block diagram showing a portion of FIG. 4 embodiment;

FIG. 12 is an illustrative view showing a portion of an operation ofFIG. 4 embodiment;

FIG. 13 is a block diagram showing a portion of FIG. 4 embodiment;

FIG. 14 is a block diagram showing a portion of FIG. 4 embodiment;

FIG. 15(A) is an illustrative view showing an output of a precoder, FIG.15(B) is an illustrative view showing an output of a hold circuit, FIG.15(C) is an illustrative view showing an output of a judgment circuit,and FIG. 15(D) is an illustrative view showing an output of a 4-codegeneration circuit;

FIG. 16 is an illustrative view showing a portion of the operation ofFIG. 4 embodiment;

FIG. 17 is an illustrative view showing a portion of the operation ofFIG. 4 embodiment;

FIG. 18 is an illustrative view showing a portion of FIG. 4 embodiment;

FIG. 19 is a waveform chart showing a frequency spectrum of a recordsignal;

FIG. 20 is a block diagram showing another embodiment according to thepresent invention;

FIG. 21 is a block diagram showing a portion of FIG. 20 embodiment;

FIG. 22 is a block diagram showing a portion of FIG. 20 embodiment;

FIG. 23 is a block diagram showing a portion of FIG. 20 embodiment;

FIG. 24 is a block diagram showing a portion of FIG. 20 embodiment;

FIG. 25 is a block diagram showing a portion of FIG. 20 embodiment;

FIG. 26 is a block diagram showing a portion of FIG. 20 embodiment; and

FIG. 27(A) is an illustrative view showing an output of a precoder, FIG.27(B) is an illustrative view showing an output of a hold circuit, FIG.27(C) is an illustrative view showing an output of a judgment circuit,and FIG. 27(D) is an illustrative view showing an output of a 4-codegeneration circuit.

BEST MODE FOR EMBODYING THE INVENTION

An embodiment described in the following utilizes facts that the numberof the kinds of codes generated in claim by inserting "0" or "1" as acontrol bit into input data and subjecting to I-NRZ modulation is alwayslimited to four (4) for the same input data, and that the four kinds ofcodes have a specific relationship to each other can be generated fromone kind of code, and that there is a predetermined rule in therelationship of the four kinds of codes.

The facts will be described with referring to FIG. 1 and FIG. 2. Asshown in FIG. 1(A) and FIG. 1(B), in a code A0 obtained by inserting "0"as the control bit into input data "a" of 24 bits and subjectinginserted data to the I-NRZ modulation and a code A1 obtained byinserting "1" as the control bit into the input data "a" and subjectinginserted data to the I-NRZ modulation, bits of odd numbers of the codesA0 and A1 have an inverted relationship. This means that second bits inthe last two bits of each code have the inverted relation. The last twobits become first two bits of a modulation signal used for the nextI-NRZ modulation. Furthermore, as understood from FIG. 2(A) and FIG.2(C), in a code B0 obtained by inserting "0" into succeeding 24 bits ofinput data "b" and subjecting inserted data to the I-NRZ modulation at atime that a preceding code is a code obtained by inserting "0" (the lasttwo bits are "00") and a code B2 obtained by inserting "0" intosucceeding input data "b" and subjecting inserted data to the I-NRZmodulation at a time that a preceding code is a code obtained byinserting "1" (the last two bits are "01") bits of even numbers of thecodes B0 and B2 have the inverted relationship.

Furthermore, as understood from FIG. 2(B) and FIG. 2(D), in a code B1obtained by inserting "1" into succeeding input data "b" and subjectinginserted data to the I-NRZ modulation at a time that a preceding code isa code obtained by inserting "0" and a code B3 obtained by inserting "1"into succeeding input data "b" and subjecting inserted data to the I-NRZmodulation at a time that a preceding code is a code obtained byinserting "1", bits of even number of the codes B1 and B3 have theinverted relationship.

Furthermore, as understood from FIG. 2(A) and FIG. 2(D), all bits of thecodes B0 and B3 have the inverted relation in the code B0 obtained byinserting "0" into succeeding input data "b" and subjecting inserteddata to the I-NRZ modulation at a time that a preceding code is a codeobtained through the "0" insertion and the code B3 obtained by inserting"1" into succeeding input data "b" and subjecting inserted data to theI-NRZ modulation at a time that a preceding code is a code obtainedthrough the "1" insertion.

In the following description, a code obtained by inserting "0" as thecontrol bit and subjecting to the I-NRZ modulation is regarded as areference code S0 (or an S0 code), a code that odd number bits have theinverted relation to with respect to odd number bits of the S0 code isregarded as an S1 code, a code that even number bits have the invertedrelation with respect to even number bits of the S0 code is regarded asan S2 code, and a code that all bits have the inverted relation to allbits of the S0 code is regarded as an S3 code. Since this relation isthe same in the last two bits of the S0 code to the S3 code, a resultobtained by inserting "0" into 24 bits following the S0 code andsubjecting to the modulation and a result obtained by inserting "1" into24 bits following the S2 code and subjecting to the modulation becomethe same, and a result obtained by inserting "1" into 24 bits followingthe S0 code and subjecting to the modulation and a result obtained byinserting "0" into 24 bits following the S2 code and subjecting to themodulation become the same. Furthermore, a result obtained by inserting"0" into 24 bits following the S1 code and subjecting to the modulationand a result obtained by inserting "1" into 24 bit following the S3 codeand subjecting to the modulation are the same, and a result obtained byinserting "1" into 24 bits following the S1 code and subjected to themodulation and a result obtained by inserting "0" into 24 bits followingthe S3 code and subjecting to the modulation are the same.

That is, as a result that three data sequentially inputted are subjectedto the I-NRZ modulation in chain, eight (8) codes can be obtained at athird time; however, it is finally no more than that two couples of fourkinds of codes can be obtained. Codes which can be obtained in afollowing data chain are always limited to four kinds of codes S0 to S3defined in the above description. Furthermore, codes linked to the S0code or the S2 code are the S0 code and the S1 code in the four kinds ofcodes, and codes linked to the S1 code or the S3 code are the S2 codeand the S3 code.

Accordingly, in the four kinds of code obtained by subjecting an inputdata train, a code obtained by inserting "0" as the control bit andsubjecting to the I-NRZ modulation is regarded as a reference code A0(or an A0 code), a code that odd number bits have the invertedrelationship to that of the A0 code is regarded as an A1 code, a codethat even number bits have the inverted relationship to that of the A0code is regarded as an A2 code, and a code that all bits have theinverted relationship to that of the A0 code is regarded as an A3 code,and if coefficients of "0" to "3" are to be added to sides of B, C, D inthe same manner in succeeding input data "b", "c"and "d", chainrelationship of the codes are shown in FIG. 3.

An embodiment described in the following is an embodiment in which atime restriction during in processing frequency components as in theprior art can be removed because it is possible to estimate the fourkinds of codes from one kind of code and the chain relationship betweena preceding code and a succeeding code is known in advance.

In the following, a case that the input data is processed at every onecode (a case of M=1) and a case that the input data is processed atevery two codes having the chain relationship will be described withassuming that a period necessary for an operation for extracting afrequency component is 25 clocks and that a period necessary for anoperation of calculation and judgment following the extraction operationis 15 clocks. First, the case that the input data is processed at everyone code is described.

With referring to FIG. 4, a coding apparatus 10 of this embodimentincludes a control bit insertion circuit 12 by which the control bit "0"of 1 bit is inserted into the input data of 24 bits. Data into which thecontrol bit is inserted is then subjected to the I-NRZ modulation in aprecoder 14, whereby the reference code S0 is generated. In addition, aninverted code signal is inputted into the precoder 14, and an operationof the precoder 14 is changed in accordance with a level of this signal.

The reference code S0 outputted from the precoder 14 is succeedinglyapplied to a delay circuit 16 and a frequency component extractioncircuit 18. The frequency component extraction circuit 18 generates theS0 code to the S3 code on the basis of the reference code S0, andoutputs frequency component extraction results of two codes in the S0code to the S3 code on the basis of a judgment result of the precedingor last code. The judgment circuit 20 judges the extraction resultsmaller than the other result, and outputs a judgment signal of a highlevel or a low level in response to a judgment result for a 4-codegeneration circuit 22 and the frequency component extraction circuit 18.In addition, a judgment signal according to the preceding or lastjudgment is also outputted from the judgment circuit 20 to the 4-codegeneration circuit 22 simultaneously.

The reference code S0 inputted into the delay circuit 16 is delayed fora time period (40 clocks) till the judgment selection signal isoutputted from the judgment circuit 20, and then applied to the 4-codegeneration circuit 22. The 4-code generation circuit 22 selects tooutput a desired code out of the reference code S0 and the S1 code tothe S3 code generated according to the code S0. In addition, an invertedcode signal is also applied to the 4-code generation circuit 22, wherebyan operation of the 4-code generation circuit 22 is changed. Anoutputted code is recorded into a magnetic tape 60 (FIG. 18) asdescribed later.

Constitution of the precoder 14 is shown in FIG. 5. The control bit anda first bit of the input data into which the control bit is inserted isinputted to one terminals of switches 24a and 24b each of which iscontrolled by the inverted code signal, and a second bit to atwenty-fourth bit of the input data are applied to one terminals of EXORcircuits 26c to 26y, respectively. Furthermore, output signals fromlatch circuits 28a and 28b outputs of which are controlled by a last twobits hold signal are applied to other terminals of the switches 24a and24b, respectively. Then, the control bit and the first bit of the inputdata are outputted from the switches 24a and 24b when the inverted codesignal is a low level, and the outputs of the latch circuit 28a and 28bare outputted therefrom when the inverted code signal is a high level,and then, the outputs are applied to the one terminals of the EXORcircuits 26a and 26b, respectively. A first bit of the reference code S0is applied to the other terminal of the EXOR circuit 26c, and a secondbit of the reference code S0 is applied to the other terminal of theEXOR circuit 26d. In the same manner, each of the outputs of the EXORcircuits is applied to the other terminal of each of the EXOR circuitsfor a bit two bits later till the EXOR circuit 26x. However, output bitsof the EXOR circuits 26x and 26y are latched by the latch circuits 28aand 28b, respectively, and outputs thereof are controlled in accordancewith the last two bits hold signal. In addition, the inverted codesignal becomes a low level when the input data is normal data, and theinverted code signal becomes a high level when the input data isparticular data used for a synchronization signal area, an overwritemargin area, and etc.

Constitution of the frequency component extraction circuit 18 is shownin FIG. 6. The S0 code outputted from the precoder 14 is applied to a DCcomponent calculation circuit 30a which operates as a Fourier transformcircuit, a frequency f1 sine component calculation circuit 30b, afrequency f1 cosine component calculation circuit 30c, a frequency f2sine component calculation circuit 30d and a frequency f2 cosinecomponent calculation circuit 30e. Then, the S1 code to the S3 code aregenerated on the basis of the S0 code, and thereafter, a sine componentand a cosine component of each of the S0 code and the S1 code or each ofthe S2 code and the S3 code are calculated in accordance with thejudgment signal, and the calculation results are outputted. S0 associatecalculation results or S2 associate calculation results out of the countresults outputted from the calculation circuits 30a to 30e are appliedto a square weighting addition circuit 32a, and S1 associate calculationresults or S3 associate calculation results therein are applied to asquare weighting addition circuit 32b. Then, an addition results isoutputted from each of the square weighting addition circuits 32a and32b, and then applied to the judgment circuit 20. In addition, S*associate calculation results means accumulated values of the frequencycomponents until an S* code (a code inputted by this time).

The judgment circuit 20 shown in FIG. 4 outputs a low level signal injudging that the square weighting addition value of the S0 associatecalculation results or the square weighting addition value of the S2associate calculation results is small, and outputs a high level signalin judging that the square weighting addition value of the S1 associatecalculation results or the square weighting addition value of the S3associate calculation results is small.

With referring to FIG. 7, the DC component calculation circuit 30aincludes DC component extraction circuits 34a to 34d for the S0 code tothe S3 code. A DC component of the S0 code applied from the precoder 14is extracted by the DC component extraction circuit 34a, and the S1 codeto the S3 code are generated on the basis of the S0 code and then the DCcomponents of the codes S1 to S3 are extracted by the DC componentextraction circuits 34b to 34d, respectively. The extracted DCcomponents are held for one code period by hold circuits 36a to 36e,respectively, and thereafter, outputs of the hold circuits 36a and 36care applied to a switch 38a, and outputs of the hold circuits 36b and36d are applied to a switch 38b. The switches 38a and 38b are controlledby the judgment signal obtained by judging the square weighting additionvalue of the preceding or last code such that two kinds of DC componentshaving a chain relationship out of the four kinds of DC components heldcan be selected. More specifically, the DC components of the S0 code andthe S1 code are selected when the judgment signal is the low level, andthe DC components of the S2 code and the S3 code are selected when thejudgment signal is the high level.

The DC components outputted from the switches 38a and 38b are applied toaddition circuits 40a and 40b, respectively, and added to accumulationresult which is obtained till the last or preceding code is outputtedfrom a switch 38c. Addition values by addition circuits 40a and 40b arethen held by hold circuits 36e and 36f, and outputs of the hold circuits36e and 36f are applied to the square weighting addition circuits 32aand 32b as the calculation results, and to the switch 38c. In addition,the switch 38c is controlled by the judgment signal which judged thesquare weighting addition value of outputs of the hold circuits 36e and36f, and selects the output of the hold circuit 36e when the judgmentsignal is the low level, and selects the output of the hold circuit 36fwhen the judgment signal is the high level. Therefore, the S0 associatecalculation result and the S1 associate calculation circuit areoutputted from the hold circuit 36e and 36f, respectively at a time thatthe judgment signal is the low level, and the S2 associate calculationresult and the S3 associate calculation result are outputted from thehold circuits 36e and 36f, respectively when the judgment signal is thehigh level.

The switches 38a to 38c are thus changed-over, and therefore, theaddition circuits 40a and 40b operate as a first addition means and asecond addition means, a third addition means and a fourth additionmeans, a fifth addition means and a sixth addition means or a seventhaddition means and a eighth addition means. Furthermore, the chainrelationship of the DC components outputted from the switches 38a and38b and the calculation results outputted from the hold circuits 36e and36f are shown in FIG. 12. More specifically, at a time that the DCcomponents of code B0 to B3 are extracted by the DC component extractioncircuits 34a to 34d, for example, if the judgment circuit 20 judges thata square weighting addition value of an A0 associate calculation resultis the smallest in the square weighting addition values of the A0associate calculation result and an A1 associate calculation result, thejudgment signal of the low level is outputted from the judgment circuit20. Therefore, the DC components of the B0 code and the B1 code areapplied to the addition circuits 40a and 40b from the switches 38a and38b, and the A0 associate calculation result is applied to the additioncircuits 40a and 40b from the switch 38c.

Accordingly, the addition circuits 40a and 40b operate as the firstaddition means and the second addition means at this time. Therefore, aB0 associate calculation result (an addition value of the DC componentof the B0 code and the A0 associate calculation result) and a B1associate calculation result (an addition value of the DC component ofthe B1 code and the A0 associate calculation result) are outputted fromthe hold circuits 36e and 36f at a next time. Furthermore, at a timethat the DC component of the C0 code to the C3 code of the succeedinginput data c are extracted, if it is judged that the square weightingaddition value of the B1 associate calculation result inputted to thejudgment circuit 20 is small, the high level signal is outputted fromthe judgment circuit 20. Therefore, the DC components of the C2 code andC3 code are outputted from the switches 38a and 38b, and the B1associate calculation result is outputted from the switch 38c.Accordingly, the addition circuits 40a and 40b operate as the thirdaddition means and the fourth addition means at this time. Therefore, aC2 associate calculation result and a C3 associate calculation resultare outputted from the hold circuits 36e and 36f at a next time.

Because of such a chain relation, the addition circuits 40a and 40boperate as the first addition means and the second addition means or thethird addition means and the fourth addition means after they operatedas the first addition means and the second addition means, and operateas the fifth addition means and the sixth addition means or the seventhaddition means and the eighth addition means after they operated as thethird addition means and the fourth addition means. Furthermore, theaddition circuits 40a and 40b operate as the first addition means andthe second addition means or the third addition means and the fourthaddition means after the operation thereof as the fifth addition meansand the sixth addition means, and operate as the fifth addition meansand the sixth addition means or the seventh addition means and the eightaddition means after the operation thereof as the seventh addition meansand the eighth addition means.

In addition, though the frequency f1 sine component calculation circuit30b, the frequency f1 cosine component calculation circuit 30c, thefrequency f2 sine component calculation circuit 30d and the frequency f2cosine component calculation circuit 30e are shown in FIG. 8 to FIG. 11,constitution of each of the calculation circuits 30b to 30e are the sameas the DC component calculation circuit 30a except that the DC componentextraction circuits 34a to 34e shown in FIG. 7 are replaced withfrequency f1 sine component extraction circuits 41a to 41d, frequency f1cosine component extraction circuits 42a to 42d, frequency f2 sinecomponent extraction circuits 44a to 44d and frequency f2 cosinecomponent extraction circuits 46a to 46d, accordingly, duplicatedescription is omitted by adding the same referring numerals for thesame point, and therefore by applying the same or similar referencenumerals to the same or similar circuits, a duplicate description willbe omitted here.

Constitution of the square weighting addition circuit 32a is shown inFIG. 13. The S0 associate calculation results or the S2 associatecalculation results outputted from the DC component calculation circuit30a, the frequency f1 sine component calculation circuit 30b, thefrequency f1 cosine component calculation circuit 30c, the frequency f2sine component calculation circuit 30d and the frequency f2 cosinecomponent calculation circuit 30e are squared by square circuits 48a to48e, respectively. Then, though an output from the square circuit 48a isjust weighted with predetermined value by a multiplication circuit 50a,outputs of the square circuits 48b and 48c are added to each other by anaddition circuit 52a, and then, weighted by a multiplication circuit50b, and outputs of square circuits 48d and 48e are also added to eachother by an addition circuit 52b, and then, weighted by a multiplicationcircuit 50c. Thereafter, outputs of the multiplication circuits 50a to50c are added to each other by an addition circuit 52c and thenoutputted to the judgment circuit 20. In addition, since a squareweighting addition circuit 30b is constituted in the same manner as thesquare weighting addition circuit 32a, a duplicate description isomitted. However, the S1 associate calculation results or the S3associate calculation results outputted from the DC componentcalculation circuit 30a, the frequency f1 sine component calculationcircuit 30b, the frequency f1 cosine component calculation circuit 30c,the frequency f2 sine component calculation circuit 30d and thefrequency f2 cosine component calculation circuit 30e are inputted tothe square weighting addition circuit 32b.

Constitution of the 4-code generation circuit 22 of FIG. 4 is shown inFIG. 14. The S0 code via the delay circuit 16 is inputted to a switch 54as it is, and applied to conversion circuits 56a to 56c to be convertedto the S1 code, the S2 code and the S3 code therein. The converted S1code to the converted S3 code are then applied to the switch 54. Switch54 is controlled by a selection switching circuit 58 which outputs acontrol signal on the basis of the inverted code signal, the lastjudgment signal and the present judgment signal, and selects and outputsone of the code to the S3 code in accordance with a table 1.

                  TABLE 1                                                         ______________________________________                                        inverted code                                                                             judgment signal                                                   signal    present time  last time                                                                              output                                       ______________________________________                                        L         L             L        S0                                                     H             L        S1                                                     L             H        S2                                                     H             H        S3                                           H         L             --       S0                                                     H             --       S3                                           ______________________________________                                    

More specifically, in a case where the inverted code signal is a lowlevel, the S0 code is outputted when both of the last judgment signaland the present judgment signal are the low levels, and the S1 code isoutputted when the last judgment signal and the present judgment signalare the low level and the high level, respectively, and the S2 code isoutputted when the present judgment signal and the present judgmentsignal are the high level and the low level, respectively, and the S3code is outputted when both of the last judgment signal and the presentjudgment signal are the high level. Furthermore, in a case where theinverted code signal is a high level, the S0 code is outputted when thepresent inverted signal is the low level, and the S3 code is outputtedwhen the present inverted signal is the high level.

An operation timing at a time that data is inputted is shown in FIG. 15.When outputting of the reference code A0 of the input data "a" from theprecoder 14 to the frequency component extraction circuit 18 isfinished, outputting of the reference code B0 of the input data "b" isstarted at a next time. Since the judgment signal is the low level inthe beginning, the switches 38a and 38b are connected to the holdcircuits 36a and 36b and the components of the A0 code and the A1 codeare outputted from the switches 38a and 38b. The judgment result for theA associate codes is determined in 15 clocks later, and the switches 38ato 38c are switched in response to the result. If the high level signalis outputted because a value of the A1 associate calculation results issmaller as a result of the judgement of the square weighting additionvalues of the A associate calculation results, the components of the B2code and the B3 code are added to each other out of the A1 associatecalculation results and four kinds of component extraction results, andthe square weighting addition values of the B2 associate calculationresults and the B3 associate calculation results are applied to thejudgment circuit 20. Furthermore, the reference code A0 inputted to the4-code generation circuit 22 with being delayed by the delay circuit 16for 40 clocks is converted into the A1 code by the last judgment signalof the low level and the present judgment signal of the high level, andthen outputted.

If the judgment circuit 20 judges that the square weighting additionvalue of the B2 associate calculation results is small at 15th clockfrom a timing that the precoder 14 begins to output the reference codeC0 of the input data "c", and then outputs the low level signal, the B2associate calculation results and the components of the C0 code and theC1 code are added to each other, and the square weighting additionvalues of the C0 associate calculation results and the Cl associatecalculation results are applied to the judgment circuit 20. Furthermore,the reference code B0 inputted to the 4-code generation circuit 22 isconverted into the B2 code by the last judgment signal of the high leveland the present judgment signal of the low level.

If the judgment circuit 20 outputs the low level signal because thejudgment circuit 20 judges that the square weighting addition value ofthe C0 associate calculation results is smaller at 15th clock from atiming that the precoder 14 begins to output the reference code D0 ofthe input data "d", the C0 associate calculation results and thecomponents of the D0 code and the D1 code are added to each other, andthe square weighting addition values of the D0 associate calculationresults and the D1 associate calculation results are applied to thejudgment circuit 20. Furthermore, since both of the last judgment signaland the present judgment signal are the low levels, the 4-codegeneration circuit 22 outputs the reference code C0 as it is.

A processing operation of the particular data that two kinds ofparticular codes are determined irrespective of the last code and usedfor the synchronization signal area, the overwrite margin area and etc.will be described. All bits have the inverted relationship about the twokinds of the particular codes RUN-A and RUN-B formats of which aredetermined by a specification for the particular data, as shown in FIG.16. More specifically, if the particular code RUN-A is assumed as thereference code S0, the particular code RUN-B is the S3 code. When theparticular data is applied to the precoder 14, the inverted code signalof the high level is applied to the switches 24a and 24b simultaneously,whereby the outputs of the latch circuits 26a and 26b are applied to theinput terminals of the EXOR circuit 28a and 28b, respectively.Therefore, a code outputted from the precoder 14 becomes the referencecode S0 (the particular code RUN-A) even if the outputs from the latchcircuits 26a and 26b are any of "00", "01", "10" and "11", as shown inFIG. 17(A) to FIG. 17(D).

In the frequency component extraction circuit 18, it is possible toprocess the particular data in the same manner as that of the S0 code tothe S3 code of the normal data by generating and processing the S0 codeby the respective component extraction circuits 34a, 40a, 42a, 44a and46a for the S0 code and by generating the S3 code by the respectivecomponent extraction circuits 34b, 40b, 42b, 44b and 46b for the S1 codeand generating the S0 code by the respective component extractioncircuits 34c, 40c, 42c, 44c and 46c for the S2 code, and by generatingthe S3 code by the respective component extraction circuits 34d, 40d,42d, 44d and 46d for the S3 code. Furthermore, the switch 54 of the4-code generation circuit 22 is switched in response to only the presentjudgment signal. More specifically, as shown in the table 1, the S0 codeis outputted from the switch 54 when the present judgment signal is thelow level, and the S3 code is outputted from the switch 54 when thejudgment signal is the high level.

By outputting one of the S0 code to the S3 code from the 4-codegeneration circuit 22 in accordance with the judgment signal outputtedfrom the judgment circuit 20 and recording on the magnetic tape 60,codes which generates a frequency spectrum as shown in FIG. 19(A) areresultingly recorded into a track 60a of the magnetic tape 60 shown inFIG. 18, codes which generates frequency spectrum shown in FIG. 19(B)are resultingly recorded into tracks 60b and 60d, and codes whichgenerates a frequency spectrum shown in FIG. 19(C) are resultinglyrecorded into a track 60c.

According to this embodiment, as is different from the prior art thatthe last two bits of the output code on the basis of the last input datais fed-back, the last two bits of the last or preceding code obtained bythe I-NRZ modulation by the precoder 14 are fed-back, and therefore,there is no time restriction in performing the extraction operation ofthe frequency component and the judgment operation. Accordingly, it ispossible to easily encode the input data.

In the embodiment shown in FIG. 4, in a case where the judgment circuit20 judges that the square weighting addition value of the B1 associatecalculation results is the smallest in the square weighting additionvalues of the B0 associate calculation results and the B1 associatecalculation results shown in FIG. 12, for example, the square weightingaddition values of the C2 associate calculation results and the C3associate calculation results are inputted into the judgment circuit 20at a next time. However, in a case where the square weighting additionsvalues of the B0 associate calculation results and the B1 associatecalculation results are approximately the same value, and the squareweighting addition values of the C1 associate calculation results is thesmallest in the square weighting addition values of the C0 associatecalculation results to the C3 associate calculation results, there is apossibility that a code outputted from the 4-code generation circuit 22is not always an optimum code. A coding apparatus 10 of anotherembodiment shown in FIG. 20 is to improve such a problem.

With referring to FIG. 20, since the coding apparatus 10 this embodimentshown is the same as the coding apparatus 10 of the embodiment shown inFIG. 4 except that a frequency component extraction circuit 61 isconstituted as shown in FIG. 21, and a delay circuit 62 is a 65 clocksdelay circuit, and a judgment circuit 63 judges on the basis of four (4)inputs, a duplicate description will be omitted by applying the samereference numerals to the same or similar points.

The frequency component extraction circuit 61 is constituted as shown inFIG. 21. That is, the S0 code outputted from the precoder 14 is appliedto a DC component calculation circuit 64a, a frequency f1 sine componentcalculation circuit 64b, a frequency f1 cosine component calculationcircuit 64c, a frequency f2 sine component calculation circuit 64d and afrequency f2 cosine component calculation circuit 64e. Then,predetermined calculation operations are performed according to thejudgment signal from the judgment circuit 20, and the S0 associatecalculation results to the S3 associate calculation results areoutputted therefrom. In these results, the S0 associate calculationresults are applied to a square weighting addition circuit 66a, and theS1 associate calculation results are applied to a square weightingaddition circuit 66b, and the S2 associate calculation results areapplied to a square weighting addition circuit 66c, and the S3 associatecalculation results are applied to a square weighting addition circuit66d. Thereafter, operation results by the square weighting additioncircuits 66a to 66d are applied to the judgment circuit 20. In addition,since the square weighting addition circuits 66a to 66d have the sameconstitution as that of the square weighting addition circuit 32a shownin FIG. 13, a duplicate description will be omitted.

With referring to FIG. 22, the S0 code outputted from the precoder 14 isapplied to DC component extraction circuits 68a to 68d. Then, though theDC component of the S0 code is extracted by the DC component extractioncircuit 68a, in the DC component extraction circuit 68b, the S1 code isgenerated on the basis of the S0 code as inputted, and then the DCcomponent of the S1 code is extracted. As is the same as the DCcomponent extraction circuit 68b, in the DC component extractioncircuits 68c and 68d, the S2 code and the S3 code are generated on thebasis of the S0 code, and then the DC components of the S2 code and theS3 code are extracted. The DC components extracted by the DC componentextraction circuits 68a to 68d are applied to hold circuits 70a to 70d,and the DC components equal to one code are held therein. Then, the DCcomponents outputted from the hold circuits 70a to 70d are added tocalculation results outputted from switches 74a and 74b in additioncircuits 72a to 72d.

More specifically, the DC component of the S0 code and the calculationresult from the switch 74a are added to each other in the additioncircuit 72a, and the DC component of the S1 code and the calculationresult from the switch 74a are added to each other in the additioncircuit 72b, and the DC component of the S2 code and the calculationresult from the switch 74b are added to each other in the additioncircuit 72c, and the DC component of the S3 code and the calculationresult from the switch 74b are added to each other in the additioncircuit 72d. The addition values outputted from the addition circuits72a to 72d are held by hold circuits 76a to 76d, respectively, and thenoutputted to square weighting addition circuits 66a to 66d as thecalculation result at a next time, respectively. Furthermore, outputs ofthe hold circuits 76a and 76c are applied to the switch 74a, and outputsof the hold circuits 76b and 76d are applied to the switch 74b. Theswitches 74a and 74b are switched in accordance with the judgment signalfrom the judgment circuit 22, and the outputs of the hold circuits 76aand 76b are outputted from the switches 74a and 74b when the judgmentsignal is the low level, and the outputs of the hold circuits 76c and76d are outputted when the judgment signal is the high level.

By changing-one the switching of the switches 74a and 74b in such amanner, the addition circuits 72a to 72d operate as the first additionmeans to the fourth addition means or the fifth addition means to theeighth addition means. Furthermore, the chain relationship of thecalculation results outputted from the hold circuits 76a to 76d is shownin FIG. 12. That is, if the judgment signal is the high level, becausethe B0 associate calculation results to the B3 associate calculationresults are outputted from the hold circuits 76a to 76d and the squareweighting addition value thereof are judged by the judgment circuit 20,for example, the switches 74a and 74b are switched for the hold circuits76c and 76d, respectively. Therefore, the B2 associate calculationresults and the B3 associate calculation results outputted from theswitches 74a and 74b are properly added to the DC components of the C0code to the C3 code outputted from the hold circuits 70a to 70d.Accordingly, the addition circuits 72a to 72d operate as the fifthaddition means to the eighth addition means at this time. Then, the C0associate calculation results to the C3 associate calculation resultsare outputted from the hold circuits 76a to 76d at the next time,respectively. Thereafter, if the judgment signal is the low levelbecause the C0 associate calculation results to the C3 associatecalculation results are judged in the same manner, the C0 associatecalculation results and the C1 associate calculation results outputtedfrom the switches 74a to 74b are properly added to the DC components ofthe D0 code to the D3 code. Accordingly, the addition circuits 72a to72b operate as the first addition means to the fourth addition means atthis time. In addition, the judgment circuit 20 outputs the low levelsignal when the square weighting addition value of the S0 associatecalculation results or the S1 associate calculation results is judged tobe the smallest, and outputs the high level signal when the squareweighting addition value of the S2 associate calculation results or theS3 associate calculation results is judged to be the smallest.

Because of such the chain relationship, the addition circuits 72a to 72doperate as the first addition means to the fourth addition means or thefifth addition means to the eighth addition means after the same operateas the first addition means to the fourth addition means, and operate asthe first addition means to the fourth addition means or the fifthaddition means to the eight addition means after the operation as thefifth addition means to the eight addition means.

With referring to FIG. 23 to FIG. 26, since the frequency f1 sinecomponent calculation circuit 64b, the frequency f1 cosine componentcalculation circuit 64c, the frequency f2 sine component calculationcircuit 64d and the frequency f2 cosine component calculation circuit64e are the same as the DC component calculation circuit 64a except thatfrequency f1 sine component extraction circuits 78a to 78d, frequency f1cosine component extraction circuits 80a to 80d, frequency f2 sinecomponent extraction circuits 82a to 82d and frequency f2 cosinecomponent extraction circuits 84a to 84d are provided instead of the DCcomponent extraction circuits 68a to 68d shown in FIG. 22, a duplicateddescription will be omitted by applying the same reference numerals tothe same or similar components.

An operation timing is shown in FIG. 27. When the outputting of thereference code A0 of the input data "a" from the precoder 14 to thefrequency component extraction circuit 61 is finished, at a next time,the outputting of the reference code B0 of the input data "b" from theprecoder 14 is started. Respective components of the A0 code to the A3code are outputted from the hold circuits 70a to 70d at the same timingas the start of the output, and then, the judgment result of the squareweighting addition value of the A associate calculation results isevaluated at 15th clock. The judgment result has no sense in a case ofthe chain of two codes, and the judgment signal maintains the low levelthereof. Therefore, the A0 associate calculation results and the A1associate calculation results are selected by the switches 74a and 74b,and then, the A0 associate calculation results and the components of theB0 code and the B1 code are added to each other by the addition circuits72a and 72b, and the A1 associate calculation results and the componentsof the B2 code and the B3 code are added to each other by the additioncircuits 72c and 72d.

The judgment result of the square weighting addition value of the Bassociate calculation results is evaluated at 15th clock from the timingthat the components of the B0 code to the B3 code are outputted from thehold circuits 70a to 70d, i.e. 15th clock from the timing that theprecoder 14 begins to output the reference code C0. If the judgmentsignal of the high level is outputted at this time because the squareweighting addition value of the B2 associate calculation results or theB3 associate calculation results is the smallest, the B2 associatecalculation results and the B3 associate calculation results areselected by the switches 74a and 74b, respectively, and then properlyadded to the components of the C0 code to the C3 code outputted from thebold circuits 70a to 70d. Furthermore, the A1 code is selected by the4-code generation circuit 22 in accordance with the present judgmentsignal of the high level and the last judgment signal of the low level,and then outputted, as understood from the table 1.

The judgment result of the square weighting addition value of the Cassociate calculation results is evaluated at 15th clock from the timingthat the components of the C0 code to the C3 code are outputted from thehold circuits 70a to 70d, that is, 15th clock from the timing that theprecoder 14 begins to output the reference code D0. When the judgmentsignal of the low level is outputted because the judgment circuit 20judges that the square weighting addition value of the C0 associatecalculation results or the C1 associate calculation results is thesmallest, the C0 associate calculation results and the C1 associatecalculation results are selected by the selection circuits 74a and 74b,and then subjected to the next addition operation. That is, the C0associate calculation results and the components of the D0 code and theD1 code are added to each other, and the C1 associate calculationresults and the component of the D2 code and the D3 code are added toeach other. Furthermore, the B2 code is outputted in accordance with thepresent judgment signal of the low level and the last judgment signal ofthe high level.

According to the FIG. 20 embodiment, since the value obtained throughthe calculation of the codes for the next input data and the squareweighting addition is judged, and the most suitable code of the datainputted before is to be outputted, it is possible to improve theproblem occurs in the coding apparatus 10 shown in FIG. 4. Morespecifically, in a case where the square weighting addition values ofthe B0 associate calculation results and the B1 associate calculationresults shown in FIG. 12 are almost the same value, and where the squareweighting addition values of the C1 associate calculation results is thesmallest in the square weighting addition values of the C0 associatecalculation results to the C3 associate calculation results, since theoperations for extracting the frequency components are executed withbeing made in chain with the B0 associate calculation results, the mostsuitable code is outputted from the 4-code generation circuit 22.

In addition, in order to further improve the problem included in thecoding apparatus 10 shown in FIG. 4, the number of the codes in chainmay be increased. In such a case, it is necessary to provide 2^(M) ofaddition circuits and hold circuits at the next stage included in thefrequency component calculation circuits and to provide 2^(M-1) ofswitches, according to the number M of the codes in chain, and tooperate the first addition circuit to the 2^(M) th addition circuit suchthat the calculation results of the frequency components can beoutputted in a chain relationship shown in FIG. 12.

Furthermore, in the above described embodiment, a code obtained byinserting "0" into the control bit and then by modulating the inserteddata is regarded as the reference code, and three codes generated on thebasis the reference code are regarded as the associate codes. However,it is clearly understood that the same operation becomes possible evenif any one of the four kinds of codes is regarded as the reference code.Even more, the number of the bits of the code is not restricted to 25bits.

Furthermore, though these embodiments are described with using theprecoder 14 of a parallel system, the present invention is notrestricted to this case, and it is clearly understood that the presentinvention can be applied to a case that a precoder of a serial system isused.

Although the present invention has been described and illustrated indetail, it is clearly understood that the same is by way of illustrationand example only and is not to be taken by way of restriction, thespirit and scope of the present invention being limited only by theterms of the appended claims.

What is claimed:
 1. A coding method, comprising the steps of:(a)inserting a control bit into input data of a predetermined number ofbits; (b) generating a first code by I-NRZ modulating the input datainto which said control bit has been inserted by said step (a); (c)generating second, third, and fourth codes in association with saidfirst code; and (d) selectively outputting one of said first, second,third, and forth codes based on frequency components of said first,second, third, and fourth codes, said step (d) including the stepsof:(d-1) extracting said frequency components of said first, second,third, and fourth codes; (d-2) outputting a judgement signal based onsaid frequency components; and (d-3) selecting one of said first,second, third, and fourth codes in accordance with said judgementsignal.
 2. A coding apparatus, comprising:insertion means (12) forinserting a control bit into input data of a predetermined number ofbits; a precoder (14) which operates a first code through I-NRZmodulation of the input data into which said control bit has beeninserted by said insertion means; associate code generation means (22,56a, 56b, 56c) for generating second, third, and fourth codes inassociation with said first code based on said first code; frequencycomponent extracting means (18) for extracting a plurality of frequencycomponents of said first, second, third, and fourth codes; judgementmeans (20) for outputting a judgement signal by comparing said pluralityof frequency components; and code outputting means (22, 54) forselectively outputting one of said first, second, third, and fourth inaccordance with said judgement signal.
 3. A coding apparatus accordingto claim 2, wherein said frequency component extraction meansincludes:first to fourth extraction means for extracting first to fourthfrequency components of each of said first to fourth codes; first tofourth calculation means for calculating each of said first to fourthfrequency components and outputting first to fifth calculation results;and first to fifth operation means for operating each of said first tofifth calculation results outputted from said first to fifth calculationmeans.
 4. A coding apparatus according to claim 3, wherein each of saidfirst to fourth extraction means includes frequency component extractionmeans for generating a first code, a second code and a third code on thebasis of said reference code and extracting predetermined frequencycomponents of said reference code, said first code, said second code andsaid third code.
 5. A coding apparatus comprising:insertion means (12)for inserting a control bit into input data, a reference code generationmeans (14) for generating a reference code through I-NRZ modulation ofdata outputted from said insertion means; associate code generationmeans (22, 56a, 56b, 56c) for generating a predetermined number ofassociate codes in association with said reference code on the basis ofsaid reference code; frequency component extracting means (18) forextracting a plurality of frequency components of said reference codeand said associate codes; judgement signal outputting means (20) foroutputting a judgement signal based on said frequency components of saidreference code and said associate codes; and code outputting means(22,54) for selectively outputting one of said reference code and saidassociate codes in accordance with said judgement signal, wherein saidfrequency component extraction means includes:first to Nth extractionmeans for extracting first to Nth (N is an integer) frequency componentsof each of said reference code and said associate codes, first to Nthcalculation means for calculating each of said first to Nth frequencycomponents and outputting first to 2^(M) th (M is a positive integer)calculation results; and first to 2^(M) th operation means for operatingeach of said first to 2^(M) th calculation results outputted from saidfirst to Nth calculation means, wherein each of said first to Nthextraction means includes frequency component extraction means forgenerating a first code, a second code and a third code based on saidreference code and extracting predetermined frequency components of saidreference code, said first code, said second code and said third code,and wherein each of said first to Nth calculating means includes:firstaddition means for adding said frequency components of said referencecode at a present time and said calculating results of said frequencycomponents of said reference code at a last time, thereby to regardaddition results as said calculation results of said first frequencycomponent of said reference code at said present time; second additionmeans for adding said frequency components of said first code at saidpresent time and said calculation results of said frequency componentsof said reference code at said last time, thereby to regard additionresults as said calculation results of said first frequency component atsaid first code at said present time; third addition means for addingsaid frequency components of said second code at said present time andsaid calculation results of said frequency components of said first codeat said last time, thereby to regard addition results as saidcalculation results of said first frequency component of said secondcodes at said present time; fourth addition means for adding saidfrequency components of said third code at said present time and saidcalculation results of said frequency components of said first code atsaid last time, thereby to regard addition results as said calculationresults of said first frequency component of said third code at saidpresent time; fifth addition means for adding said frequency componentsof said reference code at said present time and said calculation resultsof said frequency components of said second code at said last time,thereby to regard addition results as said calculation results of saidsecond frequency component of said reference code at said present time;sixth addition means for adding said frequency components of said firstcode at said present time and said calculation results of said frequencycomponents of said second code at said present time, thereby to regardaddition results as said calculation results of said second frequencycomponent of said first code at said present time; seventh additionmeans for adding said frequency components of said second code at saidpresent time and said calculation results of said frequency componentsof said third code at said last time, thereby to regard addition resultsas said calculation results of said second frequency component of saidsecond code at said present time; and eighth addition means for addingsaid frequency components of said third code at said present time andsaid calculation results of said frequency components of said third codeat said last time, thereby to regard addition results as saidcalculation results of said second frequency component of said thirdcode at said present time.
 6. A coding apparatus according to claim 5,wherein each of said firs to Nth calculation means includes first andsecond adders for outputting said first and second calculation results,first setting means for operating said first adder as said first, third,fifth and seventh addition means, and second setting means for operatingsaid second adder as said second, fourth, sixth and eighth additionmeans, in a case where M=1.
 7. A coding apparatus according to claim 5,wherein each of said first to Nth calculation means includes first tofourth adders for outputting said first to fourth calculation results,first setting means for operating said first adder as said first andfifth addition means, second setting means for operating said secondadder as said second and sixth addition means, third setting means foroperating said third adder as said third and seventh addition means, andfourth setting means for operating said fourth adder as said fourth andeighth addition means, in a case where M=2.
 8. A coding apparatusaccording to claim 5, wherein each of said first to Nth calculationmeans includes first to 2^(M) th adders for outputting said first to2^(M) th calculation results, first setting means for operating (1+8n:n=0, 1, 2, . . . , 2^(M-3))th adder as first addition means, secondsetting means for operating (2+8n)th adder as second addition means,third setting means for operating (3+8n)th adder as third additionmeans, fourth setting means for operating (4+8n)th adder as fourthaddition means, fifth setting means for operating (5+8n)th adder asfifth addition means, sixth setting means for operating (6+8n)th adderas sixth addition means, seventh setting means for operating (7+8n)thadder as seventh addition means, eighth setting means for operating(8+8n)th adder as eight addition means, in a case where M≧3.
 9. A codingapparatus according to claim 5, wherein said reference code generationmeans includes replacing means (24a, 24b) for inserting predeterminedone bit of said reference code at said last time instead of said controlbit and for inserting predetermined one bit of said reference code atsaid last time instead of a first bit of said input data.